A hardware arhitecture for rapid generation of electro-holographic
fringe patterns
John A. Watlington,
Mark Lucente, Carlton J. Sparrell, V. Michael Bove, Jr., Ichiro Tamitani
Television of Tomorrow Group
/Spatial Imaging Group
MIT Media Laboratory
Cambridge, MA
This report describes the hardware architecture and software
implementation of a hologram computing system developed at the MIT
Media Laboratory. The hologram computing employs specialized
stream-processing hardware embedded in the Cheops Image Processing
system - a compact, block data-flow parallel processor. A super
position stream processor performs weighted summations of arbitrary
one-dimensional basis functions. A two step holographic computation
method - called Hogel-Vector encoding utilizes the stream processor's
computational power. An array of encoded hogel vectors, generated from
a three-dimensional scene description, is rapidly decoded using the
processor. The resulting 36-megabyte holographic pattern is
transferred to frame-buffers and then fed to a real-time
electro-holographic display, producing three-dimensional holographic
images. System performance is sufficient to generate an image volume
approximately 100mm per side in 3 seconds. The architecture is
scalable over a limited range in both display size and computational
power. The limitations on system scalability will be identified and
solutions proposed.
Published as:
J. A. Watlington, Mark Lucente, C. J. Sparrell, V. M. Bove, I.
Tamitani."A hardware architecture for rapid generation of
electro-holographic fringe patterns" SPIE Proc. Vol. #2406:
Practical Holography IX, 2406-23, (SPIE, Bellingham, WA, 1995).