ANDI-FG Hardware Description

The ANDI-FG board is based around a Motorola 56001 Digital Signal Processor, a fully functional and fairly fast microprocessor capable of any number of computing tasks, and a Phillips SAA7191, a Digital Multistandard Decoder that does the actual digitization.

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The digitization is handled entirely by the SAA7191; when a picture is taken - by setting B8 in X:FFE5, a Port C output - the SAA7191 takes control of the external data and address buses and writes the image to the Video RAM. While this is happening, the DSP can access its internal RAM and execute code store in the internal 512-word program memory, but cannot access the 8k external P-RAM or the Video RAM. The SAA7191 (U17) decodes the information from the two A/D converters (U15 & U18) and writes it into the video ram bank (U3-6 & U8-U11). The host computer directly controls the SAA7191 registers through the I2C bus, which is accessible through an io address.

The 56001 is a 27MHz Digital Signal Processor and is capable of running arbitary user supplied code. Port A is used to access the external RAM, Port B is used for the Host Interface and Port C is configured to access the RAM-bank switching logic and to flag the SAA7191 to take a picture. The DSP has an 8-k external program memory (U13) and the video ram is visible at Y:8000 and is divided in 32-k banks.

The control logic is implemented in a Programmable Gate Array, U12.

The board has external interfaces for three seperate video inputs, only one of which can be sampled at a time, and a connector block for a high-speed serial interface, standard across many Motorola Components. This could be used, for example, to interface to a MiniBoard.