Publication

Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

Xiang Li ; Zhixian Chen ; Nansheng Shen ; Deblina Sarkar ; Navab Singh ; Kaustav Banerjee, "Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire," in IEEE Electron Device Letters, vol. 32, no. 11, pp. 1492-1494, Nov. 2011.

Abstract

For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as β€œAND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.

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