MIThril Bsedock, $Id: README,v 1.4 2002/02/06 01:38:37 rich Exp $ ## $Log: README,v $ ## Revision 1.4 2002/02/06 01:38:37 rich ## final revisions for 1.0 MHDGPLI and 6.2 revisions for README ## ## Revision 1.3 2001/11/01 05:46:06 rich ## haloween version ## ## Revision 1.2 2001/09/06 04:04:42 rich ## final(?) checkin before sending off package. ## ## Revision 1.1 2001/08/18 08:27:55 rich ## Documentation for August17 design (post minor bug-fixes, pre +5V fix). ## LICENSE TERMS License terms: This hardware design document package (comprised of the files listed below) is distributed under the terms of the GNU General Public License as published by the Free Software Foundation (either version 2 of the License, or at your option any later version) as it is construed in the "MIThril Hardware Design GPL Interpretation" version one or any later version. You may freely redistribute this document package and/or modify the hardware design under the terms of this license. This hardware design is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License and the MIThril Hardware Design GPL Interpretation along with this document package. If you did not receive a copy of the GPL, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. If you did not receive a copy of the MIThril Hardware Design GPL Interpretation, contact the MIThril team via email or in writing at 20 Ames Street, Building E15 Room 383, Cambridge, MA 02139. Overview This README file is part of the document package for version 1000-6.2 of the BrightStar ipEngine1 dock board design, which (when combined with the BrightStar ipEngine1 and appropriate software) drives the MicroOptical QVGA display and supports the MIThril body bus protocols. Since there are no programmable components that are part of this design, no software is included with this hardware document package. (The relevant FPGA code for the BrightStar ipEngine1 and linux drivers are also available, but are distributed separately. Please see the MIThril web site for more information, .) Questions and comments regarding this board design should be directed to . Release Notes Version 1000-6.2 notes: The 1000-6.2 document package fixes one major part-specification bug and a number of small documentation errors or ambiguities discovered in the process of having the design fabricated by Assembly Plus. The major bug was an incorrectly specified part number for the MicroOptical connector, resulting in the the wrong connector gender. The minor bugs include missing or ambiguous orientation information on the silk screen for LEDs and the power diode. It is important to provide adequate strain relief for the MIThril connector (the HRS3560-16S part). At a minimum, the through-hole board mounts should be filled with solder. For maximal reliability, machine screws should be added as well. Strain relief for the MicroOptical is also critical. A rubber collar should be used with the display cable, and a cable tie used to secure the collared cable to the board through the labeled "uOpt. Cable strain relief" holes. Version 1000-6.2 bugs: The silk screen printing overlaps with vias and the edges of pads in places, causing breaks in text or symbols. The DAC part is now listed by DigiKey as obsolete, so it may be necessary to find a replacement part for future fabrication runs. The 10uF polarized capacitors spec'd by the design appear not to be available through DigiKey any more, so substitutes may need to be found. Some ex-post-facto fixes were added to the silk screen on the board rather than to the part descriptions themselves, which means that care must be taken if the provided EagleCad board files are used as the basis for further board revisions. Also see "Version 1000-6 bugs," below. Version 1000-6 notes: The version 1000-6 design is functionally identical to the v1000-5 design. The v1000-6 document package fixes the documentation problems of previous versions, and includes corrected silk-screen layers for both sides of the board and properly depicts all headers and connectors on the bottom. Power routing is also slightly cleaner in this version, and like v1000-5 this design has been tested to work with both "old" and "new" style MicroOptical displays. The previously diagnosed "thermal" failure mode that prompted the delay in manufacture of v1000-5 turns out to be an FPGA clocking/bandwidth problem on the BrightStar; both v1000-5 and v1000-6 work equally well with the fixed FPGA core. The v1000-6 design adds three resistors, which allow bipolar transistors to be substituted for the MOSFET transistors Q1, Q2, and Q3 if desired. Also, this version of the design specifies that the single-row headers PWR-HDR, RS232-1, and RS232-2 be initially left unstuffed, to allow for user customization. Version 1000-6 bugs: Like the v1000-5 version, this version of the board is difficult to hand-stuff because of the fine-pitch pin spacing of the resistor arrays, capacitor arrays, and level-shifters. Silver solder and a steady hand are recommended, though some may prefer to use solder paste. If the PCB is fabricated without solder-mask (as in AP Circuits P1 fabrication) a small pice of electrical tape or other insulator is required between the ground-plane and the bottom of the UOPT-CON part to prevent the shorting of video signals to ground. The corners and edges of the PCB should be rounded and smoothed with sandpaper after fabrication to make the assembled unit friendlier for body-worn applications. Version 1000-5 notes: As of September 5, 2001, version 1000-5 is the official "production" design, but has not yet been publicly released. The v1000-5 design fixes a fabrication error and a bug in the +5V routing in version 1000-4, which resulted in a noisy +5V line and stochastic failures in some 5V peripherals. This design also results in a somewhat less noisy video signal than some previous versions. The v1000-5 document package includes a revised and corrected bill of materials and the Eagle Cad schematic and PCB files. Version 1000-5 bugs: -- IMPORTANT -- There is one known bug in the v1000-5 document package -- the following single- and double-row headers are mistakenly depicted on the top layer of the board in the schematic and PCB files: J10, J11, RS232-1, RS232-2, and PWR-HDR. All headers and connectors are mounted on the bottom of the board. The choice of some packages (the resistor arrays, for instance) make hand-stuffing the board difficult. This will be fixed in the next published version, if any. Version 1000-4 notes: As of 17 August 2001, the version 1000-4 design is tested and successfully drives the newer MicroOptical QVGA clip-on displays (as well as the old ones). However, a bug in the +5V routing and the addition of 3V/5V level shifters has added a significant amount of noise to the +5V line, which may be causing difficulties with the one-wire bus (and possibly other protocols as well). The new features of v1000-4 are the level-shifters (74LVX3245QSCF) and impedance-matching resistor and capacitor arrays. This design fixes other important (non-fatal) bugs, including reversed VIDH and VIDL signals, and a bad center voltage reference. Document Package Contents Meta Information: README . . . . . . . . . this file GPL.txt . . . . . . . . the GPL version 2 MHDGPLI.txt . . . . . . . the MIThril Hardware Design GPL Interpretation Platform Independent Design Files: (found in the rev1000-6.2 directory) bsedock.011130.sch.ps . . . . PostScript schematic bsedock.011130.brd-all.ps . . PostScript image of PCB bsedock.011130.brd-bottom.ps . PostScript image of PCB bottom layer bsedock.011130.brd-top.ps . . PostScript image of PCB top layer bsedock.011130.netlist . . . netlist bsedock.011130.partlist . . . partlist bsedock.011130.pinlist . . . pintlist bsedock.011130.scr . . . . . netscript bsedock.011130.bom . . . . . bill of materials bsedock.011130.bom-annotated . annotated bill of materials (ordering) PCB Layer Images (encapsulated PostScript, found in the rev1000-6.2 directory) bsedock.011130.cmp.ps . . . . component side bsedock.011130.sol.ps . . . . solder (bottom) side bsedock.011130.stc.ps . . . . solder mask, components side bsedock.011130.sts.ps . . . . solder mask, solder side bsedock.011130.plc.ps . . . . silk screen (top) bsedock.011130.pls.ps . . . . silk screen (bottom) Eagle Cad Design Files: (found in the rev1000-6.2 directory) bsedock.011130.sch . . . . . schematic bsedock.011130.brd . . . . . PCB Gerber Files: (found in the rev1000-6.2 directory) bsedock.011130.cmp . . . . . component side bsedock.011130.sol . . . . . solder (bottom) side bsedock.011130.stc . . . . . solder mask, components side bsedock.011130.sts . . . . . solder mask, solder side bsedock.011130.plc . . . . . silk screen (top) bsedock.011130.pls . . . . . silk screen (bottom) bsedock.011130.whl . . . . . aperture file Excellon files: (found in the rev1000-6.2 directory) bsedock.011130.drd . . . . . Excellon drill file bsedock.011130.dri . . . . . Drill station info file bsedock.011130.drl . . . . . drill list