Dissertation Title: Zeptojoule Computing: Superconducting adiabatic logic for scalable energy-efficient hardware

Abstract:
The world’s artificial intelligence data centers are on track to consume more electricity than many industrialized nations, but the silicon transistors powering them dissipate energy 10,000 times above the physical minimum dictated by thermodynamics. In contrast, the Adiabatic Quantum Flux Parametron (AQFP) is a superconducting digital logic device capable of switching at energies near this fundamental thermodynamic limit, i.e. AQFP dissipates about 10^-21 J per operation at 5 GHz. Even accounting for a ~1000 W/W cryogenic cooling overhead to maintain superconducting operation at 4 K, this represents roughly 100× lower energy dissipation than the ~10^-16 J switching energy of modern CMOS transistors. Yet superconducting digital logic has long struggled to translate device-level efficiency into practical system-level gains, hindered by the absence of dense superconducting memory, complex clocking networks that limit scalability, and, until recently, the continued dominance of Moore's law CMOS scaling.

This dissertation demonstrates how AQFP circuits can move beyond device-level promise toward system-level viability through contributions at four levels of the hardware abstraction stack. First, I develop and experimentally characterize synchronizer circuits that relax AQFP's rigid timing requirements, enabling scalable multi-clock domain designs. Second, I design, fabricate, and test a compact AQFP SR-Loop register file for low-level on-chip memory and characterize Long Josephson Junction devices as a candidate technology for future high-capacity cryogenic delay-line memories. Third, I introduce a high-throughput dataflow microarchitecture that exploits AQFP's clocked pipeline structure to achieve high compute utilization on AI workloads. Fourth, I extend established CMOS accelerator modeling tools to superconducting electronics, enabling the first quantitative full-stack comparison between AQFP and CMOS systems on real-world AI workloads. Taken together, these contributions chart a practical path toward scalable superconducting computing with the potential for orders-of-magnitude improvement in energy performance.

Committee members:
Neil Gershenfeld
Director, Center for Bits and Atoms
Massachusetts Institute of Technology

Karl K. Berggren
Faculty Head, EE and Julius A. Stratton Professor in EE and Physics
Massachusetts Institute of Technology

Vivienne Sze
Professor in Electrical Engineering and Computer Science
Massachusetts Institute of Technology