W. Cao, J. Jiang, J. Kang, D. Sarkar, W. Liu and K. Banerjee, "Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2015, pp. 12.3.1-12.3.4. doi: 10.1109/IEDM.2015.7409682

Abstract

Tunneling field-effect transistors (TFETs) are well known for their potential in low power electronics. The emerging two-dimensional (2D) semiconductors provide an excellent platform for constructing TFETs with desired properties. In this paper, by employing non-equilibrium Green's function (NEGF) based quantum transport simulations, 2D semiconductor based TFETs are innovatively designed and optimized, in terms of performance, energy efficiency, and scalability (up to 3 nm gate length, L g ) improvement w.r.t. ITRS requirements. Firstly, it is found that 2D homojunction TFETs (HMJTs) do not help in low-power very large-scale integration (VLSI), and the cause is identified to be their weak onset strength. Secondly, in order to enhance the onset strength, heterojunction TFET (HTJT) with judiciously selected material combination (WTe 2 -MoS 2 ), optimized doping concentration, and most importantly, the gated Esaki diode (GED) structure is designed. It is found that the designed TFET provides significant improvement in performance and energy efficiency w.r.t. ITRS requirements, up to L g = 9 nm. However, it is found that TFET with MoS 2 as channel material begins to suffer from source-to-drain tunneling leakage (SDTL) at L g = 6 nm, which is even earlier than that of its MOSFET counterpart. The cause is identified to be the band-to-band tunneling nature of carrier transport in TFETs in the entire operation region of interest. Thirdly, in order to overcome this scaling obstacle, broken-gap HTJT aided by innovative use of anisotropic and high effective mass 2D material (to fully exploit the advantage of the GED structure) is proposed. The proposed novel TFET is found capable of scaling up to L g = 3 nm. Furthermore, an energy-delay benchmark is provided for the proposed devices from L g = 12 nm to 3 nm. Finally, a predictive analysis is provided on the prospects of applying the proposed 2D TFETs for high-density 3D logic integration as a promising pathway for beyond L g = 3 nm, in terms of alleviating the challenging issue of thermal dissipation in 3D ICs.